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document number: mc33793 rev 13.0, 11/2006 freescale semiconductor technical data freescale semiconductor, inc. reserves the right to change the detai l specifications, as may be required, to permit improvements in the design of its products. ? freescale semiconductor, in c., 2006. all rights reserved. distributed system interface (dsi) sensor interface the 33793 is a slave distributed system interface (dsi) device that is optimized as a sensor interf ace. the device contains circuits to power sensors such as accelerometers and to digitize the analog level from the sensor. the device is controlled by commands over the dsi bus and returns measured data over the bus. features ? conforms to dsi specification version 1 ? 4-channel, 8-bit analog-to-digital converter (adc) ? 4 pins configurable as analog or logic inputs or as logic outputs ? provides regulated +5.0 v output for sensor power from bus ? additional high-drive logic output ? undervoltage fault detection and signaling ? on-board clock (no external elements required) ? field-programmable address ? default and field-programmable as a dsi daisy chain device ? recognizes reverse initialization for open bus fault tolerance ? detects short to battery on bus switch and prevents its closure ? pb-free packaging designated by suffix code ef figure 1. 33793 simplified application diagram 33793/a ordering information device temperature range (t j ) package MC33793D/r2 -40c to 150c 16 soicn mcz33793ef/r2 mcz33793aef/r2 scale 2:1 distributed system interface d suffix ef suffix (pb-free) 98asb42566b 16-pin soicn busin 33793 dsio 33790 gnd error test x y v cc gnd x-y accelerometer busin i/o0 i/o1 i/o2 h_cap regout agnd logout busrtn busout i/o3 33793 multiple dsi slaves
analog integrated circuit device data 2 freescale semiconductor 33793 device variations device variations table 1. device variations freescale part no. other significant device variations mcz33793ef/r2 existing capacity mcz33793aef/r2 capacity expansion
analog integrated circuit device data freescale semiconductor 3 33793 internal block diagram internal block diagram figure 2. 33793 simplifi ed internal block diagram io0 hcap busout busrtn logout io1 io2 io3 busin rectifiers bus switch 0 ? 35 v bi-directional forward receiver reverse receiver data frame received message from mcu bandgap reference data frame bandgap reference response current 0 ?11 ma 7.0 ma/ s oscillator 4.0 mhz logic command decode state machine response generation i/o buffers dataout <3:0> dataout <0> dataout <1> dataout <2> dataout <3> i/o<3:0> i/o0 i/o1 i/o2 i/o3 sel logic out high current buffer address a<3:0> 4 bits nvm power management 5.0 v regulator bg reference bias currents 4:1 mux adc 8 bits 4 supply comparators por undervoltage detector bg gnd bus return
analog integrated circuit device data 4 freescale semiconductor 33793 pin connections pin connections figure 3. 33793 pin connections table 2. 33793 pin definitions a functional description of each pin can be found in the functional pin description section beginning on page 10 . pin number pin name pin function formal name definition 1 busrtn power bus return this pin provides the common return for power and signalling. 2 i/o0 input/output logic i/o this pin can be used to provide a l ogic level output, a logic input, or an analog-to-digital (a/d) input. 3, 5 agnd ground analog ground this pin is the low reference level and power return for the analog-to- digital converter (adc). 4 i/o1 input/output logic i/o this pin can be used to provide a l ogic level output, a logic input, or an a/d input. 6 i/o3 input/output logic i/o this pin can be used to provide a l ogic level output, a logic input, or an a/d input. 7, 10, 13, 15 nc no connect no connect these pins have no internal connections. 8 i/o2 input/output logic i/o this pin can be used to provide a l ogic level output, a logic input, or an a/d input. 9 logout output logic out this is a logic output with higher pull-up drive capability than the standard logic i/o. 11 regout output regulator output this pin provides a regulated 5.0 v output. the power is derived from the bus. 12 h_cap output holding capacitor a capacitor attached to this pin is charged by the bus during bus idle and supplies current to run the device and for external devices via the regout pin during non-idle periods. 14 busin input dsi bus input this pin attaches to the bus and re sponds to initialization commands. 16 busout output dsi bus output this pin attaches to the bus and responds to reverse initialization commands. logout busout nc busin nc h_cap nc regout i/o2 busrtn i/o0 agnd i/o1 agnd nc i/o3 8 2 3 4 5 7 6 9 16 15 14 13 12 10 11 1
analog integrated circuit device data freescale semiconductor 5 33793 electrical characteristics maximum ratings electrical characteristics maximum ratings table 3. maximum ratings all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit electrical ratings i/o pin voltage v io -0.3 to v regout + 0.5 v i/o pin current i io 5.0 ma busin, busout, busrtn, and h_cap voltage v in -0.3 to 40 v busin, busout, busrtn, and h_cap current (continuous) i in 250 ma esd protection (1) human body model machine model v esd1 v esd2 2000 200 v thermal ratings storage temperature t stg -55 to 150 c operating junction temperature t j -40 to 150 c peak package reflow temperature during reflow (2) , (3) t pprt note 3. c thermal resistance junction to case r jc 150 c/w notes 1. esd1 performed in accordance with the human body model (c zap = 100 pf, r zap = 1500 ? ), esd2 performed in accordance with the machine model (c zap = 200 pf, r zap = 0 ? ). 2. pin soldering temperature limit is for 10 seconds maximum dura tion. not designed for immersion so ldering. exceeding these lim its may cause malfunction or permanent damage to the device. 3. freescale?s package reflow capability m eets pb-free requirements for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.freescale.com, search by part number [e.g. remove pref ixes/suffixes and enter the core id to view all orderable parts . (i.e. mc33xxxd enter 33xxx), and review parametrics.
analog integrated circuit device data 6 freescale semiconductor 33793 electrical characteristics static electrical characteristics static electrical characteristics table 4. static electric al characteristics characteristics noted under conditions -0.3 v v busin or v busout 30 v, 5.5 v < v h_cap < 30 v, -40 c < t a < 85 c unless otherwise noted. typical values noted refl ect the approximate par ameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit internal quiescent current drain v h_cap = 25 v, logout = 0, i/o = input i q ? ? 3.0 ma busin or busout to h_cap rectifier voltage drop i busin or i busout = 15 ma i busin or i busout = 100 ma v rect ? ? 0.75 0.9 1.0 1.2 v busin + busout bias current v busin or v busout = 8.0 v, v h_cap = 9.0 v v busin or v busout = 0.5 v, v h_cap = 25 v i bias -100 ? ? ? 100 20 a rectifier leakage current v busin or v busout = 5.0 v, v h_cap = 25 v i rlkg -20 ? 100 a reg0ut 5.5 v > v h_cap > 25 v, i ro = 12 ma v reg 4.75 5.0 5.25 v regout line regulation i ro = 12 ma, 5.5 v > v h_cap > 25 v vr line ? 71 180 mv regout load regulation i ro = 0 to 12 ma, 5.5 v > v h_cap > 25 v vr ld ? 2.3 100 mv undervoltage lockout proportional to unloaded v regout v uvl 0.93 0.95 0.97 v ro bus switch resistance v bi = 8.0 v, i bo = -80 ma (bus switch active) r sw ? 4.0 8.0 ? i/o0 and i/o3 pull-down current 0 < v busin or v busout < 1.0 v i pd 7.0 11 13 a i/o1 and i/o2 pull-up current v ro < v busin or v busout < v ro - 1.0 v i pu -7.0 -11 -13 a busin and busout logic thresholds low high v thl v thh 2.8 5.5 3.0 6.0 3.2 6.5 v logic duty cycle (assured by design) logic 0 logic 1 d cl d ch 10 60 33 67 40 90 % busin + busout response current v busin and/or v busout = 4.0 v i rsp 9.9 11 12.1 ma adc code conversion error (inl) adc inl ? ? < 1.0 lsb adc full-scale error adc fs ? ? 3 counts i/o logic input thresholds logic high logic low v ih v il 0.7 ? 0.54 0.51 ? 0.3 v ro
analog integrated circuit device data freescale semiconductor 7 33793 electrical characteristics static electrical characteristics i/o logic output levels output low (i l = 1.0 ma) output high (i l = -500 a) v ol v oh 0 0.8 0.08 0.985 0.5 1.0 v v ro logout output levels output low (i l = 500 a) output high (i l = -10 ma, 6.2 v < v h_cap < 25 v) output high (i l = -100 a, 6.2 v < v h_cap < 25 v) v lol v loh1 v loh2 0 4.7 ? 0.2 5.0 ? 0.5 5.3 v ro +0.5 v programming time from positive edge of busin or busout > v thh on program command to following command negative transition < v thh t prog 100 200 1000 ms nvm busin or busout programming voltage nvm vp 22.25 ? 30 v table 4. static electrical characteristics (continued) characteristics noted under conditions -0.3 v v busin or v busout 30 v, 5.5 v < v h_cap < 30 v, -40 c < t a < 85 c unless otherwise noted. typical values noted refl ect the approximate par ameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 8 freescale semiconductor 33793 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 5. dynamic electri cal characteristics characteristics noted under conditions -0.3 v v busin or v busout 30 v, 5.5 v v h_cap 30 v, -40 c t a 85 c unless otherwise noted. typical values noted refl ect the approximate par ameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit initialization to bus switch closing t bs 100 150 200 s loss of signal reset time maximum time below frame threshold t to ? ? 100 ms adc code conversion time (go, no-go test) t adc ? ? 27 s busin and busout response current transition time 1.0 ma to 9.0 ma transition, 9.0 ma to 1.0 ma t itr ? 7.0 10 ma/ s busin or busin timing to response current busin or busout negative voltage transition = 3.0 v to i rsph = 7.0 ma busin or busout negative voltage transition = 3.0 v to i rspl = 5.0 ma t rsph t rspl ? ? ? ? 3.3 3.3 s
analog integrated circuit device data freescale semiconductor 9 33793 electrical characteristics timing diagrams timing diagrams figure 4. bus switch and reset timing figure 5. response current timing t bs t to busin/busout bus switch internal reset open frame threshold frame threshold closed end of initialization command reset 9.0 ma 7.0 ma 1.0 ma 1.0 ma 5.0 ma 9.0 ma t itr t itr t rspl t rsph 3.0 v 3.0 v busin/busout response current
analog integrated circuit device data 10 freescale semiconductor 33793 functional description introduction functional description introduction the 33793 is designed to be used with a sensor at a location that is remote from a centralized mcu. this device provides power, measurement, and communications between the remote sensor an d the centralized mcu over a dsi bus. sensors such as accelerometers can be powered from the regulated output of the device, and the resulting analog value from the sensor can be converted from an analog level to a digital value for transmission over the dsi bus in response to a query from the mcu. four i/o lines can be configured by the central m cu over the dsi bus as analog inputs, digital inputs, or digital outputs. this allo ws more than one sensor to be remotely controlled and measured by a single 33793. additionally, a high drive logic output is provided that can be used to power other low-power sensors. power is passed from busin or busout through on- board rectifiers to a storage capacitor (referred to as the h_cap). the h_cap stores energy during the highest voltage excursions of the busi n or busout pin (idle) and supplies energy to power the device during low excursions of busin and busout. the regulator supplies an on-board regulated voltage for internal use, and the power on reset (por) circuit provides a reset signal during low-voltage conditions and during power up/down. some current is available for low-power sensors. data from the central control unit (ccu) is applied to the busin and/or busout pins as voltage levels that are sensed by the level detection circuitry. the serial decoder detects these transitions and decodes the incoming data. the control logic provides over all control of the 33793. it controls diagnostic testing and formats responses to commands with the message encoder. responses are formed via a switched current source that is slew-rate controlled. the one-time programmable (otp) memory array provides the nonvolatile stor age for the pre-programmed address. it is accessed via the read/write nvm command. it has a built-in hardware lock th at only allows one write. functional pin description bus return (busrtn) this pin provides the common return for power and signalling. input/output (i/o0, i/o1, i/o2, i/o3) this pin can be used to provide a logic level output, a logic input, or an analog-to-digital (a/d) input. analog ground (agnd) this pin is the low reference level and power return for the analog-to-digital converter (adc). logic out (logout) this is a logic output with hi gher pull-up drive capability than the standard logic i/o. regulator output (regout) this pin provides a regulated 5.0 v output. the power is derived from the bus. holding capacitor (h_cap) a capacitor attached to this pin is charged by the bus during bus idle and supplies current to run the device and for external devices via the regout pin during non-idle periods. dsi bus input (busin) this pin attaches to the bus and responds to initialization commands. dsi bus output (busout) this pin attaches to the bus and responds to reverse initialization commands. functional internal block description refer to figure 2 , 33793 internal block diagram, page 3 , for a simplified representatio n of the 33793?s components. rectifier this rectifier or s witch peak detects the bus signal into an external capacitor attached to h_cap. the capacitor supplies power during signaling while the input voltage is at a lower level. the voltage waveform at busin and/or busout and the size of the filter capacitor at h_cap must be such that the voltage at h_cap will not drop below the frame threshold during signaling. por the 33793 leaves the reset state when the voltage on h_cap rises above the po wer-on reset threshold. timeout a timeout timer keeps track of the length of the time when the input is not in idle mode. if this time exceeds a limit, the
analog integrated circuit device data freescale semiconductor 11 33793 functional description functional internal block description part is reset. the purpose of this is to allow the part to reset itself if the connection to the ma ster is lost or if power is removed from the system. 5.0 v regulator the 5.0 v regulator supplies intern al power for the device and also provides approximately 6.0 ma through the regout pin to power an external sensor. undervoltage detector the undervoltage detector moni tors the output voltage of the 5.0 v regulator. if the regout voltage drops too low for accurate a/d operation, a signal is sent to the control logic. the control logic will interpret this signal and, in response to a command, report a status indicating an undervoltage condition to have existed. when received, the command will clear the signal after having read the status. if the voltage is too low when the a/d conversion was completed, the returned value will be zero (binary 00000000). io pins 0 to 3 the io pins can serve as l ogic inputs, logic outputs, or analog inputs. at power-up or after a clear, the pins are all logic inputs and can be used to measure an analog level value for an analog value request command. the pins can be individually configured as logi c inputs or outputs by the io control command. if the pin is configured as a logic output, reading the analog value will return the analog level the output is being driven to. analog-to-digital converter the adc is an 8-bit successive approximation type using on-board capacitive division. it uses the clk signal from the on-board oscillator for sequencing. the adc uses regout as a full-scale reference voltage and ground agnd for a zero-level reference. the adc signals when it has made a valid conversion by asserting a signal to the controller. if this signal is not asserted when a value is being captured by the controller, the controller will signal that an invalid a/d value was obtained. the value of ?0" (binary 00000000) is reserved by the control logic to signal an error. a value of ?0? from the adc will be reported as ?1? (binary 00000001) by the control logic. serial encoder the serial encoder accepts the digitized value from the adc and formatting/data from the control logic. a logic transition from idle to signal high and then to signal low at busin will cause the first bit to be presented to the current switch (response loading). a transition to signal high and back to signal low will cause the next bit to be presented to the current switch. this will continue until a transition back to idle turns off the current switch. slew the slew circuit serves to reduce emi produced as a result of switching the bus loading current sink element. the slew circuit limits the rise and fall time of current loading the bus by controlling the current sinking element. switched current source a "1" data return bit will be signaled by turning on a fixed current source. during signaling time, the 33793 will be using power from h_cap and not loading the bus for power. the current will be drawn from eit her busin or busout or split between them. the split can be in any proportion as long as the total is correct. the current source is turned of f whenever the bus is at idle level. level detector the level detector contains comparators to determine if the busin or busout is at idle , logic high, or logic low. the inputs from busin and busout are sensed by the device so that if either side is driven by the signaling waveform while the other is not, the signaling will be detected. this circuit also provides a signal to indicate if the signal is being received on the busout pin. if a "reverse initialization" command is received, it can only be acted upon if the device is not already initialized and if the signal is present on busout. serial decoder the serial decoder monitors transitions on the busin or busout. when the 33793 is idle and supplying power to itself and the external device(s ) (via regout), the input to busin will be in the idle state. a transition from this level to signal low (through signal high) will start the process of decoding a word of data. busin is driven from signal low to signal high for each bit and back to signal low to start the next bit. the determination of whether the bit was a one or a zero is made by determining whether it spent more time low (a zero) or high (a one). the end of the word is signaled by a transition at the end of the last bit from signal high to idle. the advantage of this method is that it will a ccept data over a wide range of rates and is not dependent on an accurate clock. the controller will typically indicate a logic zero by spending 2/3 of the bit period at signal low and 1/3 at signal high. a logic one would be 1/3 of the bit period at signal low and 2/3 at signal high. control logic the control logic performs the digital operations carried out by this device. its principle functions include: ? decoding input instructions. ? control the general purpose i/o and logicout in response to busin or busout commands. ? control a/d conversions. ? form response word. ? capture and store address. ? control bussw. ? reset device on power-up. ? control the general purpose i/o logic configuration.
analog integrated circuit device data 12 freescale semiconductor 33793 functional description functional internal block description ? read the general purpose i/o logic values and respond to request for these values. ? generating a cycle redund ancy check (crc) for the received data and transmitted data in conformance with the dsi bus standard. additionally, the control logic performs error checking on the received data. if errors ar e found, no action is taken and no response is made. errors include: ? crc received doesn?t match crc of received data. ? number of received bits is not 12 or 20. clock the clock is a low-stability type with the capacitor integrated onto the die. the signaling system and all internal operations are such that no external precision timing device is needed in the normal operation of this device. bus switch (bussw) the bus switch passes signaling and power to all subsequent devices on the bus. it can block a voltage of either polarity up to the highest idle state level between busin and busout. logicout logicout is a logic level ou tput with enhanced high-side drive capability. addressing the 33793 ic supports both runtime programmable and pre-programmed addressing as defined in the dsi specification. runtime progra mmable addressing uses the daisy chain bus connection. pre-programmed devices may either be connected in daisy chain or in parallel on the bus wires. programmable address devices all power up with a device address of $0 in their address re gister and their bus switches open. in the daisy chain, if the first device receives the initialization command device on busin, it will accept the address in the command and close its switch at the end of the command. the next device in the chain will now be able to receive the initialization command on its busin and will accept the next address. this proceeds down the chain until the last device is addressed. the devices can also be initialized by the reverse initialization command if the signal is applied to busout. pre-programmed devices power up with their pre- programmed address in its address register. it will ignore all initialization commands unless the address in the command matches its pre-programmed ad dress. in this event the device stores the other information contained in the initialization command.
analog integrated circuit device data freescale semiconductor 13 33793 functional device operation operational modes functional device operation operational modes a device may be permanently programmed one time with an address using a two-command sequence. the first step is satisfied on the reception of an initialization command with address set to zero, the pa[3:0] set to the address to be programmed, and the nv bit set. this will cause the address contained in the pa[3:0] bits to be stored in the address register and the bus switch cl osed. the second step is taken when a read/write nvm command is received with the pa[3:0] bits matching the a[3:0] bits and also matching the bits stored in the 33793 address register. this will cause the 33793 to permanently store this address into an internal nvm area. messages the messages follow the format defined in the distributed systems interface specification rev 1.0 unless otherwise noted. dsi bus commands this device can recognize and respond to both long-word and short-word commands. a command word summary is shown in table 6 . sw in the ?size? column of the table indicates short-word commands and lw indicates long-word commands. short-word commands may also be sent in the long-word format. however, when these commands are sent in the long-word format, it is recommended that the data byte be sent as $00 to maintain futu re compatibility. all commands marked reserved should not be sent to 33793 slaves. table 6. dsi bus commands command size description data c3 c2 c1 c0 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 lw initialization nv bs g1 g0 pa3 pa2 pa1 pa0 0 0 0 1 sw request status ? ? ? ? ? ? ? ? 0 0 1 0 sw request value 0 ? ? ? ? ? ? ? ? 0 0 1 1 lw i/o control l3 l2 l1 l0 dr3 dr2 dr1 dr0 0 1 0 0 sw request id information ? ? ? ? ? ? ? ? 0 1 0 1 sw request value 1 ? ? ? ? ? ? ? ? 0 1 1 0 sw request value 2 ? ? ? ? ? ? ? ? 0 1 1 1 sw clear ? ? ? ? ? ? ? ? 1 0 0 0 sw request value 3 ? ? ? ? ? ? ? ? 1 0 0 1 lw read/write nvm 1 1 1 1 pa3 pa2 pa1 pa0 1 0 1 0 reserved 1 0 1 1 reserved 1 1 0 0 sw clear logic out ? ? ? ? ? ? ? ? 1 1 0 1 sw set logic out ? ? ? ? ? ? ? ? 1 1 1 0 reserved 1 1 1 1 lw reverse initialization nv bs g1 g0 pa3 pa2 pa1 pa0 legend bs = controls closing of the bus switch (1 = close). dr[3:0] = direction of i/o. 1 = output. g[1:0] = group assignment (the 33793 does not use these bits). l[3:0] = level to output on i/o if configured as outputs. lo = logic out level. pa[3:0] = bus address to set the device to. nv = allows nonvolatile address programming if set to "1".
analog integrated circuit device data 14 freescale semiconductor 33793 functional device operation operational modes long- and short-word responses the device responds to long-word commands with long-wor d responses and short-word commands with short-word responses. responses are sent during the next message followi ng the command. a long-word response summary is found in table 7 and a short-word response summary is found in table 8 , page 15 . table 7. long-word response summary cmd hex command description response 0 initialization a3 a2 a1 a0 0 0 0 bf nv bs g1 g0 pa3 pa2 pa1 pa0 1 request status a3 a2 a1 a0 0 0 0 0 nv u lo bs io3 io2 io1 io0 2 request value 0 a3 a2 a1 a0 0 0 0 0 b7 b6 b5 b4 b3 b2 b1 b0 3 i/o control a3 a2 a1 a0 0 0 0 0 l3 l2 l1 l0 dr3 dr2 dr1 dr0 4 request id a3 a2 a1 a0 0 0 0 0 v2 v1 v0 0 0 0 1 1 5 request value 1 a3 a2 a1 a0 0 0 0 0 b7 b6 b5 b4 b3 b2 b1 b0 6 request value 2 a3 a2 a1 a0 0 0 0 0 b7 b6 b5 b4 b3 b2 b1 b0 7 clear no response 8 request value 3 a3 a2 a1 a0 0 0 0 0 b7 b6 b5 b4 b3 b2 b1 b0 9 read/write nvm a3 a2 a1 a0 0 0 0 0 1 1 1 1 pa3 pa2 pa1 pa0 a reserved b reserved c clear logic out a3 a2 a1 a0 0 0 0 0 nv u lo bs io3 io2 io1 io0 d set logic out a3 a2 a1 a0 0 0 0 0 nv u lo bs io3 io2 io1 io0 e reserved f reverse initialization a3 a2 a1 a0 0 0 0 bf nv bs g1 g0 pa3 pa2 pa1 pa0 legend a[3:0] = address bits. the slave address. b[7:0] = 8-bit a/d value. bf = bus fault bs = status of the bus switch (1 = close). dr[3:0] = i/o direction bits (1 = output). g[1:0] = group assignment (the 33793 does not use these bits). io[3:0] = logic level of i/o. l[3:0] = level to output on i/o if configured as outputs. lo = logic out level at the logic out pin. nv = allows nonvolatile address programming if set to ?1?. pa[3:0] = bus address to set the device to. u = undervoltage flag. v[2:0] = version number.
analog integrated circuit device data freescale semiconductor 15 33793 functional device operation dsi commands and responses dsi commands and responses initialization command the initialization command must be sent to the 33793 before it may commence communications over the bus. the command may be used three ways. the first is to initialize a programmable address device. the second is the first step in assigning a pre-programmed address. the third is to initialize a pre-programmed device. for the first case this command is sent to address zero with the nv bit set to zero. the command will be received by the next daisy chain device with its bus switch open. reception of this command will assign the device address and group number. for the second case the initia lization command is sent the same as the first except that the nv bit is set to one. reception of the command will assign the device address and group number. a read/write nvm command then may be sent to complete the setting of a pre-programmed address. a pre-programmed device must be initialized by putting its address in both pa3:pa0 and a3:a0 fields. once a device has received an initialization command, it will ignore further initialization commands unless it has received a clear command or undergone a power-up reset. if bs = 1 and no faults are det ected, initialization will cause the bus switch to close. the command format is found in table 9 . table 8. short-word response summary command command description response 0000 initialization not valid 0001 request status nv u lo bs io3 io2 io1 io0 0010 request value 0 b7 b6 b5 b4 b3 b2 b1 b0 0011 i/o control not valid 0100 request id information v2 v1 v0 0 0 0 1 1 0101 request value 1 b7 b6 b5 b4 b3 b2 b1 b0 0110 request value 2 b7 b6 b5 b4 b3 b2 b1 b0 0111 clear no response 1000 request value 3 b7 b6 b5 b4 b3 b2 b1 b0 1001 read/write nvm not valid 1010 reserved 1011 reserved 1100 clear logic out nv u lo bs io3 io2 io1 io0 1101 set logic out nv u lo bs io3 io2 io1 io0 1110 reserved 1111 reverse initialization not valid legend b[7:0] = 8-bit a/d value. bs = status of the bus switch (1 = close). lo = logic out level at the logic out pin. io[3:0] = logic level of i/o. nv = allows nonvolatile addres s programming if set to ?1?. pa[3:0] = bus address to set the device to. u = undervoltage flag. v[2:0] = version number. table 9. initialization command format data address command crc nv bs g1 g0 pa3 pa2 pa1 pa0 a3 a2 a1 a0 0 0 0 0 x3 x2 x1 x0
analog integrated circuit device data 16 freescale semiconductor 33793 functional device operation dsi commands and responses initialization response this response message is sent during the next message following a valid initialization command to the addressed device. the response is shown in table 10 . because this is a long-word only command, the short-word response is invalid. request status command this command will cause the addressed device to return the status of the nv, u, and bs bi ts and the logic levels of the i/o and logicout. the comm and format is found in table 11 . request status response this response message is sent during the next message following a valid request status command to the addressed device. the response format is found in table 12 . the high byte is omitted during the shor t-word response. no response is generated if the command address field was $0. request value n command this command will cause the analog level at one of the four i/o lines to be measured and returned on the following command. the command format is found in table 13 . the analog input measured is defined in table 14 . legend a[3:0] = address bits. the slave address. bs = bus switch position (1 = closed). g[1:0] = group bits (unused). nv = nonvolatile memory write. the value of the nv bit in the slave. pa[3:0] = bus address to set the device to. x[3:0] = cyclic redundancy check (crc ). the crc as calculated by the master. table 9. initialization command format table 10. initialization response format high byte low byte crc a3 a2 a1 a0 0 0 0 bf nv bs g1 g0 pa3 pa2 pa1 pa0 x3 x2 x1 x0 legend a[3:0] = address bits. the slave address. bf = bus fault. bus out short to battery detected. bs = bus switch position (1 = closed). g[1:0] = group bits (unused). nv = nonvolatile memory write. the value of the nv bit in the slave. pa[3:0] = bus address to set the device to. x[3:0] = cyclic redundancy check (crc). the crc as calculated by the slave. table 11. request status command format data address command crc ? ? ? ? ? ? ? ? a3 a2 a1 a0 0 0 0 1 x3 x2 x1 x0 legend a[3:0] = address bits. the address of the selected device. an address value of "0000" is ignored by all devices. x[3:0] = cyclic redundancy check (crc). the crc as calculated by the master. table 12. request status response format high byte low byte crc a3 a2 a1 a0 0 0 0 0 nv u lo bs io3 io2 io1 io0 x3 x2 x1 x0 legend a[3:0] = address bits. the slave address. bs = bus switch position (1 = closed). lo = logic out driven level. io[3:0] = values at logic i/os. nv = nonvolatile memory write. the value of the nv bit in the slave. u = undervoltage indicated true by a ?1?. x[3:0] = cyclic redundancy check (c rc). the crc as calculated by the slave.
analog integrated circuit device data freescale semiconductor 17 33793 functional device operation dsi commands and responses request values response this response is an 8-bit value representing the value measured by the adc. the selecti on of ?n? is a function of the command. this is shown in table 15 . the read will be completed during the idle period and will represent the voltage at the end of the command. if an undervoltage condition exists at any time during the command or the measurement has not completed properly, a value of ?00000000? will be returned. this is a reserved value to indicate a problem with the measurement. the minimum valid level reported will be ?00000001?. no response is generated if the command address field was $0. i/o control command this register controls the i/o ports. when the ?dr? bits are set, the corresponding i/o is enabled as an output. the ?l? bit settings control the level of t he corresponding i/o if it is enabled as an output. the format of this command is shown in table 16 . i/o control response the response indicates which i/o has been configured as outputs and their current values. the values returned will be the values programmed. the values at the pins will not be the ones that were programmed if the pin has been forced to the opposite state. the response format is shown in table 17 . no response is generated if the command address field was $0. table 13. request value n command format data address command crc ? ? ? ? ? ? ? ? a3 a2 a1 a0 c3 c2 c1 c0 x3 x2 x1 x0 legend a[3:0] = address bits. the address of the selected device. an address value of "0000" is ignored by all devices. c[3:0] = command number. x[3:0] = cyclic redundancy check (crc). the crc as calculated by the master. table 14. analog input selection command a/d input 0010 i/o0 0101 i/o1 0110 i/o2 1000 i/o3 table 15. request values response format high byte low byte crc a3 a2 a1 a0 0 0 0 0 d7 d6 d5 d4 d3 d2 d1 d0 x3 x2 x1 x0 legend a[3:0] = address bits. the address of the selected device. an address value of "0000" is ignored by all devices. d[7:0] = measured value (msb = d7). x[3:0] = cyclic redundancy check (crc). table 16. i/o control command format data address command crc l3 l2 l1 l0 dr3 dr2 dr1 dr0 a3 a2 a1 a0 0 0 1 1 x3 x2 x1 x0 legend a[3:0] = address bits. dr[3:0] = i/o direction bits. 1 = output. all bits are set to ?0? by reset/clear. l[3:0] = level to output on i/o if confi gured as output. all bits are set to ?0? by reset/clear x[3:0] = cyclic redundancy check (crc ). the crc as calculated by the master. table 17. i/o control response format high byte low byte crc
analog integrated circuit device data 18 freescale semiconductor 33793 functional device operation dsi commands and responses request id command this command will cause the device id information to be read from internal storage and returned to the master during the response to the next me ssage. the command format is found in table 18 . request id response this response message is sent during the next message following a valid long-word request id command to the addressed device. the response format is found in table 19 . the high byte is omitted during the short-word response. no response is generated if the command address field was $0. clear command this command will open the bus switch and reset all registers to the reset state. the command format is found in table 20 . no response is generated for the clear command. read/write nvm command if the nv bit has been set by a previous initialization command and the nvm has not been programmed previously, this command will permanently program the device?s one-time programmable address and return the programmed value during the next message time. once programmed, this nonvolatile address is used to set the device address register on the next and all subsequent power-ups. if the device is not blank, this command will return the programmed value during the next message time. programming the nvm address to $0 is allowed. this ensures that the device always acts as a dynamically a3 a2 a1 a0 0 0 0 0 l3 l2 l1 l0 dr3 dr2 dr1 dr0 x3 x2 x1 x0 legend a[3:0] = address bits. dr[3:0] = i/o enabled as outputs (1 = enabled as output). l[3:0] = programmed values. x[3:0] = cyclic redundancy check (crc). the crc as calculated by the slave. table 17. i/o control response format table 18. request id command format data address command crc ? ? ? ? ? ? ? ? a3 a2 a1 a0 0 1 0 0 x3 x2 x1 x0 legend a[3:0] = address bits. the address of the selected device. an address value of ?0000? is ignored by all devices. x[3:0] = cyclic redundancy check (crc ). the crc as calculated by the master. table 19. request id response format address status data crc a3 a2 a1 a0 0 0 0 0 v2 v1 v0 0 0 0 1 1 x3 x2 x1 x0 legend a[3:0] = address bits. the slave address. v[2:0] = device version number. th e silicon version number of the device. for this device the device type is 00011 as indicated by the lowest bits. x[3:0] = cyclic redundancy check (c rc). the crc as calculated by the slave. table 20. clear command format data address command crc ? ? ? ? ? ? ? ? a3 a2 a1 a0 0 1 1 1 x3 x2 x1 x0 legend a[3:0] = address bits. the address of the selected device. an address value of ?0000? clears all devices. x[3:0] = cyclic redundancy check (crc ). the crc as calculated by the master.
analog integrated circuit device data freescale semiconductor 19 33793 functional device operation dsi commands and responses addressable device and would be immune to any inadvertent future nvm programming sequences. reads and writes are long-word commands only. the command format is found in table 21 . read/write nvm response this response message is sent during the next message following a valid read/write nvm command to the addressed device. the response format is found in table 22 . the high byte is omitted during the shor t-word response. no response is generated if the command address field was $0. clear logic out command the clear logic out command sets the logic out pin to a logic low. the compliment to this command is the set logic out. the logic out is also cleared at power-up or following a clear command. the format of the clear logic out command is shown in table 23 . clear logic out response this response message is sent during the next message following a valid clear logic out command to the addressed device. the response is shown in table 24 . no response is generated if the command address field was $0. table 21. read/write nvm command format data address command crc 1 1 1 1 pa3 pa2 pa1 pa0 a3 a2 a1 a0 1 0 0 1 x3 x2 x1 x0 legend a[3:0] = address bits. these bits are the address of the device previously sent with the initia lization command. they must match the address in the pa[3:0] field and the address stored in the device address register. pa[3:0] = program address bits. these bits are the address that is to be programmed into the slave. x[3:0] = cyclic redundancy check (crc ). the crc as calculated by the master. table 22. read/write nvm response format high byte low byte crc a3 a2 a1 a0 0 0 0 0 1 1 1 1 pa3 pa2 pa1 pa0 x3 x2 x1 x0 legend a[3:0] = address bits. the slave address. pa[3:0] = programmed address bits. the address that was programmed into the nvm address bits of the slave. x[3:0] = cyclic redundancy check (crc) . the crc as calculated by the slave. table 23. clear logic out command format data address command crc ? ? ? ? ? ? ? ?- a3 a2 a1 a0 1 1 0 0 x3 x2 x1 x0 legend a[3:0] = address bits. the address of the selected device. x[3:0] = cyclic redundancy check (crc) . the crc as calculated by the master. table 24. clear logic out response format high byte low byte crc a3 a2 a1 a0 0 0 0 0 nv u lo bs io3 io2 io1 io0 x3 x2 x1 x0 legend a[3:0] = address bits. the slave address. bs = bus switch position (1=closed). lo = logic out driven level. io[3:0] = values at logic i/os. nv = nonvolatile memory write. the value of the nv bit in the slave. u = undervoltage indicated true by a ?1?. x[3:0] = cyclic redundancy check (c rc). the crc as calculated by the slave.
analog integrated circuit device data 20 freescale semiconductor 33793 functional device operation dsi commands and responses set logic out command the set logic out command sets the logic out pin to a logic high. the compliment to this command is the clear logic out. the logic out is cleared at power-up or following a clear command. the format of the clear logic out command is shown in table 25 . set logic out response this response message is sent during the next message following a valid set logic out command to the addressed device. the response is shown in table 26 . no response is generated if the command address field was $0. reverse initialization the reverse initialization is similar to the initialization command and will only work under the condition that it has not already been initialized. the command may be used three ways. the first is to initialize a programmable address device. the second is the first step in assigning a pre- programmed address. the third is to initialize a pre- programmed device. for the first case this command is sent to address zero with the nv bit set to zero. the command will be received by the next daisy chain device with its bus switch open. reception of this command will assign the device address and the group number. reception of this command will also cause the bus switch to clos e if bs = 1 and no fault is detected. for the second case the initialization command is sent the same as the first except that the nv bit is set to one. reception of the command will assign the device address and the group number and cause t he bus switch to close if bs = 1 and there are no faults. a read/write nvm command then may be sent to complete the setting of a pre- programmed address. a pre-programmed device must be initialized by putting its address in both pa3:pa0 and a3:a0 fields. once a device has received a reverse initialization command, it will ignore further reverse initialization commands or initialization comm ands unless it has received a clear command or undergone a power-up reset. the command format is found in table 27 . table 25. set logic out command format data address command crc - - - - - - - - a3 a2 a1 a0 1 1 0 1 x3 x2 x1 x0 legend a[3:0] = address bits. the address of the selected device. x[3:0] = cyclic redundancy check (crc) . the crc as calculated by the master. table 26. set logic out response format high byte low byte crc a3 a2 a1 a0 0 0 0 0 nv u lo bs io3 io2 io1 io0 x3 x2 x1 x0 legend a[3:0] - address bits. the slave address. bs = bus switch position (1=closed) io[3:0] = values at logic i/os. lo = logic out driven level. nv = nonvolatile memory write. the value of the nv bit in the slave. u = undervoltage indicated true by a ?1?. x[3:0] = cyclic redundancy check (crc). the crc as calculated by the slave. table 27. reverse initialization command format data address command crc nv bs g1 g0 pa3 pa2 pa1 pa0 a3 a2 a1 a0 1 1 1 1 x3 x2 x1 x0
analog integrated circuit device data freescale semiconductor 21 33793 functional device operation dsi commands and responses reverse initializa tion response this response message is sent during the next message following a valid reverse initialization command to the addressed device. the response is shown in table 28 . since this is a long-word only command, the short-word response is invalid. no response is generated if the command address field was $0. legend a[3:0] = address bits. these bi ts are the slave address. for programmable devices these bits are all set to zero. for pre- programmed devices these bits contain the pre-programmed address and must match the pa[3:0] bits. g[1:0] = group bits. these bits ar e the group number for the slave. these bits are not used by this device and should be set to ?0?. pa[3:0] = program address bits. t hese bits are the address that is to be stored into the slave?s address register. nv = nonvolatile memory write. when set to a one, this bit allows a subsequent nvm command to store a nonvolatile address. when set to a zero, nvm programming is disallowed. once a permanent address has been stored in the device, setting the nv bit to a one has no effect. x[3:0] = cyclic redundancy check (crc ). the crc as calculated by the master. table 27. reverse initialization command format table 28. reverse initialization response format high byte low byte crc a3 a2 a1 a0 0 0 0 bf nv bs g1 g0 pa3 pa2 pa1 pa0 x3 x2 x1 x0 legend a[3:0] = address bits.the slave address. bf = bus fault. busin short to battery detected. bs = controls closing of the bus switch (1=close). g[1:0] = group bits. not used on this part, will be set to ?0?. the group number programmed into the slave. nv = nonvolatile memory write. the value of the nv bit in the slave. pa[3:0] = bus address to set the device to. x[3:0] = cyclic redundancy check (crc) . the crc as calculated by the slave.
analog integrated circuit device data 22 freescale semiconductor 33793 typical applications typical applications communication format dsi messages are composed of individual words separated by a frame delay. transfers are full duplex. command messages from the master occur at the same time as responses from the slaves. slave responses to commands occur during the next command message. this allows slaves time to decode the command, retrieve the information and prepare to send it to the master. a bus traffic example is shown in figure 6 . the example shows three commands separated by the minimum frame delay followed by a command after a longer delay. figure 6. bus traffic example io0 h_cap busout busrtn logout regout io1 io2 io3 busin rectifiers bus switch 0 ? 35 v bi-directional forward receiver reverse receiver data frame received message from mcu bandgap reference data frame bandgap reference 1.0 f typical response current 0 ?11 ma 7.0 ma/ s oscillator 4.0 mhz logic command decode state machine response generation i/o buffers dataout <3:0> dataout <0> dataout <1> dataout <2> dataout <3> i/o<3:0> i/o0 i/o1 i/o2 i/o3 sel logic out high current buffer address a<3:0> 4 bits nvm power management 5.0 v regulator bg reference bias currents 4:1 mux adc 8 bits 4 supply comparators por undervoltage detector bg gnd 4.7 f bus return master slave
analog integrated circuit device data freescale semiconductor 23 33793 typical applications in case there is a bus error (due to induced noise or a bus fault), both the master and slave devices will read bad data. the slave reacts to bad data by not sending a response during the next frame. the master will detect a crc error once it receives the corrupted data sent by the slave, and once again when the slave fails to respond. this is illustrated in figure 7 . when this error occurs, the system software needs to acknowledge this condition and resend a command (any command of same size) so that it can receive the previous response just prior to the bus fault condition (in this case, command n). failure to take corrective action will result in unintended errors as shown in figure 7 . in this case, the master will miss responses n+1 and n+2 and will mistake them for n+3 and n+4. the master should send another n+1 command after the error is acknowledged to re-synchronize the command- response sequence. figure 7. bus traffic with receive errors (master reads incorrect data) power up reset when power is first applied to the dsi bus, the system must allow enough time for the internal 5 volt regulator of each device to come up to a proper level. this implies that h_cap must charge up to v rect + 5 v, or approximately 6 volts. the time this takes is a function of the size of h_cap, and the current drive of the master. the following equation can be used to estimate the minimum time to wait before sending an initialization command: t min ? (h_cap x 6v) / i charge where i charge is the charging current provided by the dsi master. the above assumes a daisy-chain type of bus topology, and enough time must be allowed for all down-stream devices in the chain to charge up. for example, if device #1 has it?s switch closed after it s initialization command, then the system must wait for devi ce #2 to power up before sending its initialization command, and so on down the line. if the devices are attached in a parallel or point-to-point bus configuration, then the total capacitor value is the sum of all h_caps. in addition to the charge up time, enough time must be allocated for the bu s fault test (see next section). bus faults a bus fault is defined as an external voltage on the ?inactive side? of the bus swit ch that is greater than 3v (typical). inactive refers to the side of the bus that is not yet connected to the bus. just before a device is forward initialized, the inactive side is defined as busout. similarly, just before a device is revers e initialized, the busin is defined as the inactive side. the test for a bus fault is only performed once during forward or reverse initialization (when bs bit is set) by applying an 11ma pull-down current to the inactive side of the bus switch and monitoring the vo ltage. the fault test takes approximately 200us. if no fault is detected, the bus switch will be closed, and if a fault is detected, the bus switch will not close. the fault test applies to both programmed and unprogrammed devices. exception: in the case of a daisy-chain bus topology where the last device busout line c onnects to busin of the first device (loop-back), then the f ault test will not be executed since both busin and busout are connected to active busses. it is up to the system so ftware to run the appropriate diagnostic tests to resolve this special case. (one alternative is to use a separate dsi master to handle the loop-back signal path. this second dsi mast er is only activated in the case of a bus fault so that t he last device can be accessed by means of a reverse initialization.) global address 0 any time an initialization or reverse initialization command is sent to the 33793 with an address of 0x0 (global address), the device behaves as follows: ? device initializes to address 0. ? bus switch remains open. this implies that in a daisy- chain bus topology, all devices past the first device will remain off. ? nv and bs bits are not stored and have no effect. command n bus error command n+1 command n+2 response n-1 response n no response response n command n+3 command n+4 response n+3 crc error crc error error crc master slave data misinterpreted by master
analog integrated circuit device data 24 freescale semiconductor 33793 typical applications ? device will respond to further commands at address 0 (such as setting and clearing the i/o bits and logout) but there is no response (master will read all zeros). if the devices are connected in a daisy chain, then only the fist device will respond. ? subsequent writes to re-ini tialize the device will not be possible until the device is cleared.
analog integrated circuit device data freescale semiconductor 25 33793 packaging package dimensions packaging package dimensions for the most current package revision, visit www.freescale.com and perform a keyword search using the ?98a? listed below. ef suffix (pb-free) 16-pin plastic package 98asb42566b issue m
analog integrated circuit device data 26 freescale semiconductor 33793 revision history revision history revision date description of changes 12.0 8/2006 ? implemented revision history page ? converted to freescale format ? added pc33793ef ? added feature bullets ? rewrote and enhanced device operation - no electrical changes ? updated to the prevailing freescale form and style ? removed pc33793ef and replaced with mcz33793ef/r2 in the ordering information block 13.0 11/2006 ? added mcz33793aef/r2 to the ordering information ? added device variations table on page 2 ? removed peak package reflow temperature during reflow (solder reflow) parameter from maximum ratings on page 5 . added note with instructions to obtain this information from www.freescale.com .
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